1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus (commonly called an IC tester) which can be suitably used in testing a semiconductor device, particularly a semiconductor integrated circuit (hereinafter referred to as an IC) which is a typical example of semiconductor devices.
2. Description of the Related Art
FIG. 4 shows a general configuration of a conventional semiconductor device testing apparatus (hereinafter referred to as an IC tester) for testing an IC such as a semiconductor memory element, for instance. This IC tester comprises a timing generator TG, a pattern generator PG, a waveform shaping device FC, a logical comparator DC, and a failure analysis memory FM.
The timing generator TG supplies a reference timing clock to the pattern generator PG and other various portions. The pattern generator PG outputs a pattern generation command (PAT.sub.ABC) by which a test pattern signal to be applied to an IC to be tested (IC under test, commonly called DUT) 10 is to be generated and an expected value data (EXP.DATA) by which an expected value signal to be applied to the logical comparator DC is to be generated, and supplies those signals to the waveform shaping device FC.
The waveform shaping device FC produces a test pattern signal PAT to be applied to the IC under test 10 and an expected value signal EXP to be applied to the logical comparator DC based on the pattern generation command and the expected value data supplied from the pattern generator PG. A write/read operation of a test pattern signal into/from the IC under test 10 is controlled by a control signal (CNTL.SIG) supplied via the waveform shaping device FC such that the writing operation of a test pattern signal supplied from the waveform shaping device FC into the IC under test 10 and the reading operation of data written into the IC therefrom are alternately repeated.
The data read out of the IC under test 10 is compared with an expected value data in the logical comparator DC to detect whether or not there is a discord between both signals. The failure analysis memory FM stores, every time a discord is detected in the logical comparator DC, a failure data, representing an occurrence of failure at the same address thereof as that of the IC under test 10 where that failure has occurred. To this end, the same address signal (ADR.SIG) as that applied to the IC under test 10 for reading the data therefrom is given to the failure analysis memory FM from the pattern generator PG. An failure analysis of the IC under test can be performed by reading the stored failure data in the failure analysis memory FM therefrom after the completion of the test.
The foregoing shows the whole configuration or construction and the operation of the IC tester. The present invention relates to an improvement of a device which is commonly called a pin unit in this technical field, the pin unit being provided for each of pins (terminals) of an IC under test 10. An object of the present invention is to enable a high speed operation of an IC tester by use of a simple construction of a pin unit.
FIG. 5 shows a general circuit arrangement of a conventional pin unit provided for each of pins of an IC under test. Since each pin unit may have the same configuration with one another, a circuit arrangement of a pin unit for only one pin is shown in FIG. 5.
The pin unit UN comprises a pattern generator PG, a waveform shaping device FC, a logical comparator DC, a failure analysis memory FM, a driver DR for writing an analog signal from the waveform shaping device FC into an IC under test 10, a H-logic (high-logic) comparator CPH and an L-logic (low-logic) comparator CPL.
There is provided in the pattern generator PG a pattern memory in each address of which are stored, for example, a pattern generation command "1" (PAT.sub.ABC ="1") for applying a logical waveform having logical "1" (logical H or H-logic) to a pin of the IC under test 10, a pattern generation command "0" (PAT.sub.ABC "0") for applying a logical waveform having logical "0" (logical L or L-logic) to a pin of the IC under test 10, an expected value data "L" (PAT.sub.ABC ="L") representing that an expected value signal is logical L, an expected value data "H" (PAT.sub.ABC ="H") representing that an expected value signal is logical H, and an expected pattern generation command "Z" (PAT.sub.ABC ="Z") representing that an expected value signal is high impedance, and the like. Those pattern generation commands and expected value data are read out from the pattern generator PG in the sequence specified by a pattern generating program.
A pattern generation command PAT.sub.ABC and an expected value data read out of the pattern generator PG are supplied to the waveform shaping device FC where a test pattern signal PAT (see FIG. 6C) having an analog waveform corresponding to the pattern generation command and an expected value signal EXP are produced or created. The test pattern signal PAT is inputted to one of the pins of the IC under test 10 via the driver DR. The expected value signal EXP is supplied to the logical comparator DC.
Moreover, the waveform shaping device FC further outputs a driver control signal DRE for controlling the state of the driver DR in addition to the test pattern signal PAT.
The driver control signal DRE is applied to a control terminal of the driver DR to control it such that the state of an output terminal of the driver DR is switched to an output mode or to a high impedance mode (inhibition of output mode). Specifically, during the output mode where the driver DR outputs a test pattern signal PAT, as shown in FIG. 6E, the driver control signal DRE applied to the control terminal of the driver DR remains, for example, logical H to maintain the output terminal of the driver DR in active state. On the other hand, during the high impedance mode where the data written into the IC under test 10 is read out therefrom, the driver control signal DRE applied to the control terminal of the driver DR remains, for example, logical L to maintain the output terminal of the driver DR in high impedance state (state of inhibition of output or inactive state).
During the read-out mode where the data is read out of the IC under test 10 (while the state of the output terminal of the driver DR is in the high impedance mode), the H-logic comparator CPH determines whether a logical level of the waveform of the data read out of the IC under test 10 has the normal logical H level H.sub.ref or not and outputs a decision signal SH, whereas the L-logic comparator CHL determines whether a logical level of the waveform of the data read out of the IC under test 10 has the normal L logical level L.sub.ref and outputs a decision signal SL.
Specifically, as shown in FIG. 7, the H-logic comparator CPH outputs logical 0 when the electric potential of a signal S.sub.IC read out from the IC under test 10 is higher than the normal logical H level H.sub.ref and outputs logical 1 in other conditions. On the other hand, the L-logic comparator CPL outputs logical 0 when the electric potential of the signal S.sub.IC is lower than the normal logical L level L.sub.ref and outputs logical 1 in other conditions. Further, the decision signals SH and SL are actually stamped out by strobe pulses STRB1 and STRB2 (see FIG. 6F) respectively, that is, the decision signals SH and SL are ANDed with the strobe pulses STRB1 and STRB2, respectively, and the results of decisions at the time points when the strobe pulses STRB1 and STRB2 are applied are outputted as the decision signals SH and SL, respectively.
The logical comparator DC are supplied with the decision results SH and SL from the comparators CPH and CPL, and compare the decision results SH and SL with the expected value signals EXP provided from the waveform shaping device FC. Every time the decision result SH or SL does not coincide with the corresponding expected value signal EXP, a failure data of, for instance, logical "1" representing a failure occurrence is written in the same address of the failure analysis memory FM as that of the IC under test 10 where the failure has occurred. For example, in case the address of the IC under test 10 where the failure has occurred is the address "2", logical "1" is written in the address "2" of the failure analysis memory FM.
FIG. 8 further shows in detail the circuit configuration of the section of the waveform shaping device FC and the logical comparator DC of the pin unit UN.
The waveform shaping device FC comprises a waveform memory WFM into which a pattern generation command PAT.sub.ABC (in this example, a command of 3 bits) from the pattern generator PG is inputted, a combination circuit of gate group (in this example, consisting of four AND gates and two OR gates) and a first set/reset flip-flop SRFF1 for producing a test pattern signal PAT on the basis of output signals from the waveform memory WFM, and a combination circuit of gate group (in this example, consisting of two AND gates) and a second set/reset flip-flop SRFF2 for producing a driver control signal DRE on the basis of output signals from the waveform memory WFM.
There are previously stored in the waveform memory WFM, in this example, waveform data T1S and T2S each of logical H, waveform data T1R and T2R each of logical L, waveform data T3L and T4T for defining a logical level of the driver control signal DRE, waveform data EXP1, EXP1Z, EXP2 and EXP2Z each of which defines a logical level of the expected value signal, and the like.
When the waveform data T1S of logical "H" is read out of the waveform memory WFM in response to a pattern generation command of logical "1" from the pattern generator PG, the rising portion of the waveform data T1S is stamped out by a clock pulse T.sub.1 in the associated AND gate, that is, the rising portion of the waveform data T1S is ANDed with the clock pulse T.sub.1 in the associated AND gate so that a pulse T1 is formed as shown in FIG. 6B. This pulse T1 is given to a set terminal S of the first set/reset flip-flop SRFF1 thereby generating an output of logical "1" from the first set/reset flip-flop SRFF1 at the leading edge of the pulse. That is, the timing of the leading edge (rise) of a test pattern signal PAT having a real waveform (see FIG. 6C) is defined.
Next, when the waveform data T1R of logical "L" is read out of the waveform memory WFM in response to a pattern generation command of logical "0" from the pattern generator PG, the rising portion of the waveform data T1R is stamped out by a clock pulse T.sub.1 in the associated AND gate, that is, the rising portion of the waveform data T1S is ANDed with the clock pulse T.sub.1 in the associated AND gate so that a pulse T1' is formed as shown in FIG. 6B. This pulse T1' is given to a reset terminal R of the first set/reset flip-flop SRFF1 thereby inverting the output of logical "1" of the first set/reset flip-flop SRFF1 to logical "0" at the leading edge of the pulse. That is, the timing of the trailing edge (fall) of the test pattern signal PAT having a real waveform is defined.
Though it is not shown in FIG. 6, in case waveform data T2S, T2R are read out of the waveform memory WFM, like the above-described case, the rising portions of these waveform data T2S, T2R are stamped out by a clock pulse T.sub.2 in the associated AND gates, respectively, to be given to the set terminal S and reset terminal R of the first set/reset flip-flop SRFF1 so that a test pattern signal PAT having a real waveform is generated from the first set/reset flip-flop SRFF1.
In addition, in a write mode where a test pattern signal PAT is written into an IC under test, the waveform data T3L is read out of the waveform memory WFM in response to a pattern generation command from the pattern generator PG, and the rising portion of the waveform data T3L is stamped out by a clock pulse T.sub.3 in the associated AND gate, that is, the rising portion of the waveform data T3L is ANDed with the clock pulse T.sub.3 in the associated AND gate so that a pulse T3 is formed as shown in FIG. 6D. This pulse T3 is given to a set terminal S of the second set/reset flip-flop SRFF2 thereby generating an output of logical "1" from the second set/reset flip-flop SRFF2 at the leading edge of the pulse. That is, the timing of the leading edge (rise) of a driver control signal DRE having a real waveform (see FIG. 6E) is defined.
Also, the waveform data T4T is read out of the waveform memory WFM in response to a pattern generation command from the pattern generator PG, and the rising portion of the waveform data T4T is stamped out by a clock pulse T.sub.4 in the associated AND gate, that is, the rising portion of the waveform data T4T is ANDed with the clock pulse T.sub.4 in the associated AND gate so that a pulse T4 is formed as shown in FIG. 6D. This pulse T4 is given to a reset terminal R of the second set/reset flip-flop SRFF2 thereby inverting the output of logical "1" of the second set/reset flip-flop SRFF2 to logical "0" at the leading edge of the pulse. That is, the timing of the trailing edge (fall) of the driver control signal DRE having a real waveform is defined.
The logical comparator DC comprises, in this example, two AND gates supplied with expected value signals EXP1 and EXP1Z to respective non-inverting inputs thereof respectively, further two AND gates supplied with expected value signals EXP2 and EXP2Z to respective non-inverting inputs thereof respectively, and an OR gate for multiplexing output signals from these four AND gates to supply the multiplexed signal to the failure analysis memory FM. Also, the output SH of the H-logic comparator CPH is supplied to respective the other non-inverting inputs of the AND gates to which the expected value signals EXP1 and EXP1Z are supplied, and the output SL of the L-logic comparator CPL is supplied to respective the other non-inverting inputs of the AND gates to which the expected value signals EXP2 and EXP2Z are supplied. Further, the other inputs of the AND gates to which the expected value signals EXP1Z and EXP2Z are supplied are inverting inputs.
The logical comparator DC compares the expected value signal EXP1 or EXP1Z with a decision signal SH outputted from the H-logic comparator CPH, or the expected value signal EXP2 or EXP2Z with a decision signal SL outputted from the L-logic comparator CPL. When the expected value signal does not accord with the decision signal, that is, when the signal S.sub.IC outputted from the IC under test 10 does not coincide with the level of the expected value signal, the logical comparator DC outputs a failure data of logical "1" via the OR gate, which is written in the failure analysis memory FM.
The operation speed of the IC tester described above is determined by a period T shown in FIG. 6. As one of methods for making the operation speed higher, there has been heretofore provided a method called a pin multiplex method in this technical field. This pin multiplex method is arranged such that a test is carried out by preparing the circuit arrangement for one pin shown in FIGS. 5 and 8 by two sets for one pin, and by operating two waveform shaping devices FC in the two sets in time division basis to produce a test pattern signal having a high speed or rate by two times, and by operating two logical comparators DC in the two sets in time division basis to perform their logical comparison operations at a high speed or rate by two times.
In case of operating an IC tester at high speed of twice the normal speed by use of this pin multiplex method, two sets of pin units UN are used for one pin and hence a problem occurs that the number of pins of an IC under test which are testable at one time is reduced to half.
As is well known, since an IC tester is manufactured such that the number of testable pins of an IC under test at one time is determined in advance, there is a limitation on the number of pin units UN prepared in each IC tester, that is, the number of pin units previously prepared in each IC tester is limited to a fixed number. As mentioned above, if two sets of pin units are used for one pin to perform a high speed test of an IC, the number of pins of an IC under test which are simultaneously testable at high speed is reduced to half of the number of pins of that IC in the normal speed test. Accordingly, there is a need that a high speed test is carried out twice, resulting in a drawback that a high speed test cannot be actually attained by such a pin multiplex method.